The present invention relates generally to memories, and more specifically to a method for reducing the time for initializing a memory upon power-up.
When an integrated circuit, is turned on, internal circuitry must be initialized before the integrated circuit can operate properly and communicate with external circuitry. This requirement is particularly true for an integrated circuit that is a dynamic random access memory (DRAM).
Conventionally, DRAMs are initialized by precharging digit lines and capacitor electrodes with a voltage generator in a manner that is well known to persons skilled in the art. There are significant RC delays associated with precharging the digit lines and capacitor plates to a reference voltage with the voltage generator to permit normal operation. The external circuitry, such as a microprocessor, has to wait for these steps before accessing the DRAM. As a result, operations, such as mathematical manipulation of data from the DRAM, may be delayed. There is a need to more quickly enable, or power-up, the DRAM such that it is available for use more quickly upon power-up. There is a further need to accomplish a quicker initialization of the DRAM without the addition of complex, space consuming circuitry. There is yet a further need to more quickly initialize the DRAM safely such that it is enabled in a known state.
The present invention solves the above-mentioned problems in the art and other problems which will be understood by those skilled in the art upon reading and understanding the present specification. The present invention provides a method and apparatus for initializing a memory device. In particular, the present invention allows a dynamic random access memory (DRAM) device to be powered up more quickly by using amplifiers and equilibration circuits to assist a voltage generator in pre-charging memory cell capacitors and digit lines to a desired voltage prior to normal operation of the DRAM. When the capacitors and digit lines are initially charged, an internal RAS (Row Address Signal) pulse is generated to drive pairs of digit lines to opposite rails. The equilibration circuits then equalize the digit line pairs and assist in charging the memory cell capacitors. Because the sense amplifiers and equilibration circuits supply more current than the voltage generator, the digit lines and memory cell capacitors are charged to a voltage of Vcc/2 much more quickly than with the voltage generator alone.
In one embodiment, after one or more of the internal RAS pulses are asserted, voltages on a digit line pair are amplified with a sense amplifier to voltages of zero and Vcc. Then, the amplified voltages on the digit line pair are equilibrated with an equilibration circuit to equalize the voltages on the digit lines to Vcc/2. The equilibrated voltage is also coupled through the equilibration circuit to charge a common plate of the memory cell capacitors.
By using the sense amplifier and equilibration circuit to charge the digit lines and common plate, the enablement time of the memory is significantly reduced. In some instances, it can be reduced to less than one-half of a microsecond from 20 microseconds. Furthermore, no additional circuitry is required in existing DRAM designs to reduce enablement time. The sense amplifier and equilibration circuits are already used in DRAMs. Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.